(1) Field of the Invention
The present invention relates to the forming of multilevel interconnects in the manufacture of integrated circuits in general, and in particular, to a method of employing electron beam writing in the lithography used for forming such interconnects.
(2) Description of the Related Art
Commensurate with the advances made in the ultra large scale integration (ULSI) of circuits and chips, higher resolution lithography methods are required. As is known in the art, optical lithography is limited to somewhat less than 1 micrometer (.mu.m) resolution with a registration capability of about .+-.0.3 .mu.m. To extend the capability of the lithographic pattern transfer process beyond these limits, alternatives to optical lithography have been developed, including electron beam (e-beam) lithography which offers a resolution of 0.375 .mu.m with .+-.0.3 .mu.m registration. It is disclosed in this invention, a method of employing e-beam lithography judiciously in the forming of densely packed multi-level interconnects.
Conventionally, a semiconductor chip contains one or more metal wiring layers that are separated from each other by an insulating layer and are further separated by still another insulating layer from the devices that are formed near the surface of the semiconductor that forms the base of the chip. The wiring stripes are connected to each other and to the devices at the appropriate places by means of holes that are filled with metal through the insulating layers. The holes that connect the metal lines to each other through the insulating layer are called via holes, while the holes that reach the underlying devices through its insulating layer are called contact holes. Typically, the holes are etched into an insulating layer after the latter has been deposited on the semiconductor substrate on which the chips are fabricated. It is common practice to next blanket deposit metal on the insulating layer thereby filling the holes and then forming the metal lines by etching through a patterned photo resist formed on the metal layer. For the first metal layer, electrical contact is made with the underlying devices through contact holes that allow the metal to descend through the dielectric insulator to the devices. For the second and subsequent wiring layers, the process is repeated and the contact between the metal layers is made through via holes that allow the metal to descend to the lower metal layer(s). It is also common practice to fill the holes separately with metal to form metal plugs first, planarize or smoothen them next with respect to the surface of the insulating layer and then deposit metal layer to make contact with the via plugs and then subtractively etch as before to form the required "personalized" wiring layer.
In forming wiring layers, blanket metal must be patterned. Photolithography is a common approach wherein patterned layers are usually formed by spinning on a layer of photoresist, projecting light through a photomask with the desired pattern onto the photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist, and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered soluble (positive resist) and be washed away, or insoluble (negative resist) and fix the pattern. In either case, the remaining resist on the surface forms the desired pattern.
Etching of metal lines require precise lithographic processes. The nature of the mask used for etching can affect the lithographic process itself. Thus, when photoresist is used as the mask, its local thickness can vary depending upon the underlying features that it crosses on the substrate. If it crosses a step, for example, then its thickness over the top of the step will be much thinner than that which crosses over low-lying regions. During lithographic exposure, either the thin resist becomes overexposed, or the thicker resist underexposed. Upon development, a resist pattern crossing a step will therefore exhibit a linewidth variation (i.e., narrower on the top of the step). For lines in which step heights approach the size of the linewidth, as would be the case with submicron technologies of ULSI, such variations in dimension can become unacceptable. Also, the thickness of the resist may be governed by other factors as well. For example, a photolithographic equipment, such as an G-line stepper might specify a resolution of 0.7 .mu.m. On the other hand, its depth of focus may be no more than 1 .mu.m. To achieve step coverage and satisfy the requirements of an etching process that does not exhibit extremely high selectivity, a resist layer may have to be 1.5 thick, with the result that the specified resolution of 0.7 .mu.m cannot be achieved.
This tradeoff between the depth of focus on the one hand and step coverage/selectivity on the other hand can be avoided by utilizing phase-shifting mask as disclosed by Leroux in U.S. Pat. No. 5,407,785. In the same patent, ultra-small equal-width lines and spaces are generated on an integrated circuit wafer using multiple exposure and phase-shifting at the wafer level. In particular, as shown in FIG. 1a, an integrated circuit wafer (10) is coated with a layer of photoresist (20) and then masked using a mask (30) defining a pattern of multiple feature lines arranged at a regular line pitch. The layer of photoresist is then underexposed (40) so as to partially bleach portions of the layer of photoresist in accordance with the pattern. Next, the mask and the integrated circuit wafer are positionally translated, or shifted (50) relative to one another by a predetermined fraction of the line pitch, and the layer of photoresist is then again underexposed. Developing the photoresist layer creates a stepped profile (25). The layer of photoresist is then blanket exposed (45), the stepped profile causing exposure in the vicinity of steps to be retarded. The layer of photoresist is then developed, producing thin lines of photoresist separated by substantially equal spaces of no photoresist.
Jeng, et al., in U.S. Pat. No. 5,741,624 also disclose a method using a phase shift mask for improved resolution in a semiconductor interconnect process. A semiconductor wafer having a first layer and overlying insulating layer receives a photoresist layer. A first photoresist area is exposed to light having a first dosage, while a second, adjacent photoresist area is concurrently exposed to light having a second dosage. The first area and second area then are concurrently developed to partially expose the photoresist layer. The partial exposure removes photoresist within the first area to one depth and within the second area to a second depth. The second depth differs from the first depth. In one embodiment, the second depth extend through the photoresist down to the insulating layer. After subsequently performing a contact and/or trench etch through the exposed insulating layer and removing excess photoresist above the insulating layer, conductive material is deposited in the contact/trench opening and over the insulating layer. The result is an upper conductive layer coupled to the first layer via a contact or other conductive connection.
Garofalo, et al., show a phase shift mask in U.S. Pat. No. 5,308,721 used to form a step pattern in a photoresist layer utilizing one exposure. The photoresist layer is developed to form a multi-step opening. The multi-step opening shape is then transferred to the underlying layer using etch steps. Ulrich, on the other hand, discloses a multiple exposure masking system in U.S. Pat. No. 5,753,417, for forming multi-level resist profiles as applied to a dual damascene process. A refractory metal capped dual damascene interconnect is disclosed by Cote, et al., in U.S. Pat. No. 5,262,354 where contrast enhanced photolithography is used. Another method of producing interconnects in a semiconductor device is shown by Okazaki, et al., in U.S. Pat. No. 4,31,984. Here, that region of a resist film in which a contact is to be formed and that regions thereof in which an interconnection is to be formed are respectively irradiated with an electron beam in a dose substantially equal to an optimum dose of the resist film and in a dose less than the optimum dose. Thereafter, the resist film is developed. By performing dry etching, an opening extending to a substrate is provided in the region in which the contact is to be formed, and the surface of an insulating film overlying the substrate is exposed in the region in which the interconnection is to be formed. After depositing a conductive metal film on the whole surface the remaining resist film is removed together with the metal film deposited thereon, whereby the contact and the interconnection are formed.
Not using a mask, and being able to "write" directly on the surface to be patterned would of course be a much preferred method inasmuch as the attendant problems of precise transferring image from one mask to another, and the registration of one mask with respect to the other would be alleviated. As is known in the art, electron beam lithography provides such a capability by using a focused electron beam. Such beams can readily be scanned and accurately positioned on a semiconductor substrate to expose radiation-sensitive resist (e-beam resist). That is, e-beam lithography provides the ability to produce submicron features directly on a substrate, without the use of a mask, under the control of a computer. Though quite slow in throughput (and more expensive) when compared to optical projection and step and repeat systems, it is becoming more and more necessary to use e-beam lithography as the minimum feature size of critical dimension of the ultra scale integration exceeds the limitation of optical methods. What is needed is a judicious use of the e-beam technology in order to realize the high potential of especially the highly miniaturized interconnects of the ultra scale integrated circuit technology as disclosed in the embodiments of this invention.